Platform overview

AI coverage analysis for RTL verification teams.

From UCDB export to ranked test recommendations in one pipeline. No changes to your simulation scripts, no proprietary instrumentation — Photoniq reads the coverage artifacts your simulator already produces and returns a scored manifest of what to write next.

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How it fits together

Photoniq slots into your existing EDA flow.

No proprietary simulation hooks. No Makefile changes. Photoniq reads the coverage artifacts your simulator already exports via standard UCDB or SAIF format. Your simulation environment stays exactly as it is.

RTL Source .sv / .v files Simulator VCS / Questa Xcelium UCDB Export sim.ucdb SAIF / VCD Photoniq AI coverage engine gap analysis + ranking Ranked Test Manifest phnq-manifest.json 10+ recommendations your existing RTL no changes needed standard formats one CLI command version-control friendly

Capabilities

Four tools. One coverage problem.

Photoniq predicts which tests to write — it does not run simulation for you, replace your constrained-random environment, or generate executable testbench code. The output is a ranked manifest that guides your DV team's directed-test work.

Coverage Gap Detection

  • Identifies uncovered toggle, line, FSM, and functional coverage bins
  • Cross-correlates gap patterns across modules
  • Highlights plateau zones most likely to contain functional bugs

Test Vector Ranking

  • Outputs ranked list of test scenarios by predicted coverage impact
  • Confidence scores from 0.0 to 1.0 per recommendation
  • Maps each recommendation to specific uncovered RTL bins

Yield Impact Modeling

  • Correlates floorplan block positions with manufacturing defect density
  • Flags layout decisions likely to reduce yield before tape-out
  • Links high-yield-risk zones to functionally uncovered RTL regions

Simulator Compatibility

  • Reads standard UCDB (Questa/VCS) and SAIF export formats
  • Tested with VCS, Questa, Xcelium, and Riviera-PRO
  • One CLI command — no changes to simulation scripts

Simulator support

Works with the simulators your team already runs.

Photoniq reads standard UCDB and SAIF export formats. No proprietary hooks, no simulator-vendor lock-in. If your simulator can write a UCDB file, Photoniq can read it.

VCS (Synopsys) Questa (Siemens EDA) Xcelium (Cadence) Riviera-PRO (Aldec) UCDB Format SAIF Export SystemVerilog Verilog

Export command example

Terminal 
$ phnq analyze --ucdb ./coverage/sim.ucdb --rtl ./src/rtl
✓ UCDB loaded · 12,847 bins · 34 modules
✓ RTL indexed · 48,213 lines
⚠ 3 critical uncovered regions detected
✓ Analysis complete · Results in phnq-manifest.json

Coverage gaps don't guess. Neither should you.

Start with the Explore tier — free, one project, no commitment. Or talk to us about your tape-out timeline.

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