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Photoniq Product

LVS and optical loss verification — nothing more, nothing less.

Photoniq is a verification tool, not a simulator. We don't replace Lumerical or RSoft. We fill the gap those tools leave: layout-versus-schematic and optical loss checks that catch errors before your mask order, not after characterization.

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verification summary 
Platform:  Photoniq v1.4
Engines:   LVS · Optical Loss · Mode Check
PDK:       AIM_300mm_v3.1
Format:    GDS-II · OASIS · SPICE
─────────────────────────────────
LVS        ✓ PASS   ports:14
DRC        ✓ PASS   rules:248
LOSS       ⚠ WARN   +0.8dB excess
MODE       ✗ FAIL   1 mismatch
Core Engines

Four verification engines. One report.

Every engine is purpose-built for silicon photonics. Not adapted from CMOS EDA.

Engine 01

LVS Engine

Layout-versus-schematic for photonic integrated circuits. Extracts connectivity from your GDS layout and compares it against your SPICE or Virtuoso netlist. Identifies unconnected ports, missing terminations, and routing errors that standard EDA LVS tools can't catch in optical layers.

Engine 02

Optical Loss Checker

Waveguide propagation loss, coupling loss, and insertion loss budget calculation from the PDK rule deck. Flags circuits where cumulative optical loss exceeds the design budget before simulation. Uses transfer matrix method for fast multi-segment evaluation.

Engine 03

Mode Mismatch Detector

Eigenmode expansion at every waveguide junction. Checks TE0/TM0 mode field overlap between adjacent segments. Width discontinuities, material transitions, and taper geometry are all evaluated against the PDK adiabatic transition criteria.

Engine 04

Verification Report Generator

Structured JSON + HTML verification report for every job. Each error entry includes: error type, cell path, GDS layer, coordinate, severity level, and a plain-language suggested fix. Ready for fab submission review and team sign-off workflows.

Scope Definition

Photoniq is a verification tool, not a simulator.

We built Photoniq for engineers who are tired of tools that try to do everything. Clear scope = trustworthy output.

What Photoniq does
Layout-versus-schematic for PIC connectivity
PDK rule deck compliance checks
Optical loss budget from layout geometry
Mode field overlap at all junctions
Coupling gap and taper geometry checks
Structured pass/fail report for fab review
What Photoniq deliberately does not do
FDTD / BPM / EME full-physics simulation
Device-level optimization or parameter sweeps
PDK authoring or foundry rule deck creation
S-parameter extraction from geometry
Layout generation or automated PIC routing
CMOS transistor-level verification
Report Format

The output engineers actually use

Every verification job produces a structured JSON report. Machine-readable for CI/CD pipelines. Human-readable for design review meetings.

JSON — verification report 
{
  "job_id": "PNQ-2A8F-20260315",
  "pdk": "AIM_300mm_v3.1",
  "status": "FAIL",
  "summary": {
    "errors": 1, "warnings": 2, "passed": 4
  },
  "errors": [
    {
      "id": "E001",
      "error_type": "MODE_MISMATCH",
      "severity": "ERROR",
      "cell": "TOP/edge_coupler_v2/wg_taper",
      "layer": "Si_core (1/0)",
      "coordinate": { "x_um": 4823.4, "y_um": 2190.1 },
      "message": "Width discontinuity at junction: 500nm → 220nm. TE0 overlap=0.71, threshold=0.85",
      "suggested_fix": "Insert adiabatic taper ≥ 25um, half-angle ≤ 3.2° between 500nm and 220nm segments."
    }
  ],
  "warnings": [
    {
      "id": "W001",
      "error_type": "COUPLING_INEFFICIENCY",
      "severity": "WARNING",
      "cell": "TOP/ring_add_drop/coupler_N",
      "layer": "Si_core (1/0)",
      "coordinate": { "x_um": 1204.7, "y_um": 834.2 },
      "message": "Coupling gap 185nm, PDK nominal 200nm. Excess insertion loss: +0.8dB",
      "suggested_fix": "Increase coupling gap to 198–202nm range for PDK nominal coupling."
    },
    {
      "id": "W002",
      "error_type": "TAPER_ANGLE_ERROR",
      "severity": "WARNING",
      "cell": "TOP/splitter_1x2/branch_L",
      "layer": "Si_core (1/0)",
      "coordinate": { "x_um": 2891.0, "y_um": 1102.5 },
      "message": "Taper half-angle 4.8° exceeds adiabatic limit 3.2° for 450nm→800nm transition",
      "suggested_fix": "Extend taper length to achieve ≤ 3.0° half-angle. Minimum recommended: 38um."
    }
  ]
}
Specifications

Technical specifications

Specification Details
Layout formats GDS-II (v5+), OASIS
Schematic formats SPICE netlist (.sp, .spi), Cadence Virtuoso CDF export, Lumerical INTERCONNECT .icp netlist
Output formats JSON (structured errors), HTML (human review), CSV (for fab submission), PDF (optional)
PDK configuration JSON config API for custom foundry rule decks. Version-pinned per job.
Minimum feature size Configurable per PDK. Tested down to 100nm waveguide width (SOI platforms)
Processing time 5–30 minutes typical. Scales with circuit element count. Priority queue on Professional+ plans.
API access REST API (HTTPS). Python SDK (pip install photoniq). CLI (photoniq-cli).
Supported platforms SOI (silicon-on-insulator), SiN (silicon nitride), SiGe, III-V overlay platforms
Waveguide modes TE0, TM0 primary. Multi-mode excitation analysis for TE1, TM1 at relevant widths.
Data handling GDS data processed in isolated job containers. No persistent storage of design files after report delivery.