Our mission
We built Photoniq because coverage plateau is a solved problem waiting for the right model.
Coverage escapes at tape-out are almost always in the 10–15% zone that random simulation couldn't reach. We spent years on DV floors watching teams lose weeks trying to get past 85% without a systematic approach. That problem has a solution — it just required the right training data and the right representation of RTL structure.
Our story
Santa Clara, 2024. Four people who'd spent eight years watching the same problem recur.
Hiroshi Watanabe spent eight years as a verification engineer and EDA tool developer. He'd debugged the coverage plateau problem across a processor core project, two memory controller tapeouts, and a network-on-chip design. Each time, the last 10% cost as much human time as the first 90%. He concluded the problem was tractable with the right AI model and the right coverage corpus.
Priya Raghavan was at an AI accelerator company working on graph neural network applications to circuit design. When she and Hiroshi compared notes, it became clear that GNN representations of RTL structure were exactly the right approach to the coverage prediction problem Hiroshi had been thinking about. They started building in the summer of 2024.
Devlin Marsh and Mina Osei joined early — Devlin brought deep EDA integration experience from building simulation data pipelines at a verification IP company; Mina brought the DV engineer's perspective on what a recommendation output actually needs to look like to be actionable on the floor, not just accurate on paper.
We raised initial angel funding in February 2026 to deepen the coverage prediction model and expand UCDB compatibility across more simulator variants. We are deliberately focused on one problem: the coverage plateau. We will solve it completely before expanding scope.
Team
Four people. One problem.
Eight years in RTL verification and EDA tool development. Spent those years debugging coverage plateaus across processor, memory controller, and interconnect tapeouts before concluding the problem needed an AI approach.
ML researcher with deep background in graph neural networks applied to circuit netlists. Previously worked on AI accelerator verification at a fabless chip company. Designed Photoniq's RTL structure encoder.
Senior software engineer specializing in EDA tool integrations and high-throughput simulation data pipelines. Built simulator coverage parsers at a verification IP company. Owns the CLI and API infrastructure.
DV engineer focused on SystemVerilog constrained-random testbench development. Joined Photoniq to work on the customer integration side of the platform, translating model outputs into actionable testbench changes.
Backing
Backed by angel investors. Building deliberately.
In February 2026, we closed initial angel funding to deepen the coverage prediction model and expand simulator compatibility beyond Questa and VCS. We are not chasing growth metrics — we're focused on one problem and one product until it works well enough to matter at tape-out.
We picked Santa Clara because the semiconductor verification community is here. Half of our early users are within 10 miles of the office. Being in proximity to the teams we're building for is not incidental — it's how we learn what the tool needs to do next.
FOUNDER'S NOTE
"Random simulation plateaus at 85% and everyone on the DV floor knows it. We built a model that reads your coverage database and tells you the next test to write. That's it."
— Hiroshi Watanabe, Co-Founder & CEO