We're hiring

Build the tools chip engineers actually want to use.

We're a small team in Santa Clara working on one specific hard problem. If you have deep domain knowledge in hardware verification, ML on graph-structured data, or EDA infrastructure — and you prefer real problems over pitch-deck problems — we'd like to talk.

How we work

What it's actually like here.

What we value

Deep domain knowledge
The tool has to work on real DV floors. Surface-level understanding of hardware verification doesn't get you there. We hire people who know the problem cold.
Direct feedback
We're four people. There's no organizational buffer. When something isn't working, we say so and fix it the same week. If that's uncomfortable, this isn't the right fit.
Ownership without ego
You'll own a real piece of the product — not a sub-sub-feature. We expect you to make calls, be wrong sometimes, learn fast, and not need consensus on every decision.
Talk to users constantly
The best features we've built came from sitting with a verification lead while they tried to use the tool. Engineers here talk to customers directly.

What to expect

Team size

Four people right now. You'll be employee 5 or 6. Your decisions will be visible and consequential immediately.

Location

Santa Clara, CA is preferred for engineering roles — we have a small office and user visits happen in person. Remote is possible for the right candidate with semiconductor DV background.

Compensation

Competitive cash + meaningful equity. We don't hide the numbers — we'll share the full comp picture in the first conversation.

Interview process

Intro call (30 min) → technical conversation (60 min, no whiteboard, real problems) → meet the team (2 hours on-site or remote). Decision within 5 business days.

Open roles

Three positions open now.

Senior ML Engineer — RTL Coverage Model
Santa Clara, CA / Remote Full-time

Own the coverage gap prediction model: architecture, training pipeline, accuracy metrics, and evaluation framework. You'll work with RTL corpora, UCDB-annotated datasets, and graph-based representations of hardware design. Required: deep experience with GNNs or sequence models on structured data, Python, PyTorch. Bonus: prior exposure to hardware description languages or EDA toolchains.

Apply
Senior Verification Engineer
Santa Clara, CA Full-time

Deep domain expertise in SystemVerilog DV, coverage methodology, and EDA tool integration. You'll validate Photoniq's recommendations against real tape-out RTL, own the customer integration experience, and contribute to the training data corpus. Required: 5+ years DV experience, proficiency with VCS or Questa, UCDB familiarity. Bonus: constrained-random testbench architecture experience.

Apply
Full-Stack Engineer
Santa Clara, CA / Remote Full-time

Own the web platform, API, and CLI infrastructure. You'll work across the Python FastAPI backend, the React frontend, and the phnq CLI tool. Required: production experience with Python APIs and React, comfort with async systems and job queues. Bonus: prior experience building developer tooling or CLI applications.

Apply

Don't see your role?

If you have background in semiconductor verification, EDA infrastructure, or ML on hardware data and none of the above fits — write to us anyway.