Engineering Notes
Engineering Notes from the Photoniq Team
Coverage closure methodology, UCDB analysis, yield prediction from layout decisions, and simulator-specific notes. Written for verification engineers who already know the basics.
The 85% Coverage Plateau: Why Random Simulation Runs Out of Ideas
Every chip team knows the feeling: coverage climbs fast for the first week of simulation, then slows to a crawl. Here's the engineering reason why — and what it means for your tape-out schedule.
UCDB Anatomy: What Your Coverage Database Actually Stores
A technical walkthrough of the UCDB schema — what toggle, line, FSM, and functional coverage bins map to in the file format, and why this structure matters for AI-guided analysis.
What Does a Week of Directed-Test Writing Actually Cost?
We surveyed DV engineers at chip companies about how long manual directed-test writing takes for specific coverage closure scenarios. The numbers surprised us.
Connecting Layout Choices to Yield Loss: An Engineer's Guide
How density rules, aspect ratios, and metal layer assignments during floorplan translate into measurable yield impact — and why EDA tools rarely surface this early enough.
Formal Verification vs. Simulation: A Practical Boundary Guide
Both tools live on a DV team's bench, but picking the wrong one for a property wastes weeks. A practical guide to where bounded model checking, unbounded formal, and simulation each pay off.
RTL Coverage Metrics: What 100% Line Coverage Actually Means (And Doesn't)
Line coverage at 100% can still hide entire categories of bugs. A breakdown of the six coverage metric types and which ones matter most for bug-escape risk.
What AI Models Actually Work for RTL Coverage Prediction
We tried graph neural networks on netlist DAGs, transformer-based sequence models on RTL tokens, and hybrid approaches. Here's what worked, what didn't, and why.
VCS, Questa, Xcelium: Coverage Database Export Differences That Matter
UCDB is a standard, but each simulator vendor interprets edge cases differently. A practical comparison of coverage database exports from the three major simulators, with sample schema diffs.
Closing Functional Coverage Under Tape-Out Pressure
When the tape-out window shrinks from 8 weeks to 4, how do you prioritize which coverage holes to close? A framework for triage under real schedule pressure.
Photoniq Closes Angel Funding to Accelerate AI Coverage Analysis
We raised initial angel funding to deepen our coverage prediction model and expand simulator compatibility. A note on where we're headed.
How Photoniq Ranks Test Vectors: The Score Behind the List
A transparent look at how the Photoniq coverage model assigns priority scores to test vector candidates — the inputs, the inference logic, and how to interpret the output.
Verification at AI Chip Startups: What's Actually Hard in 2025
Custom accelerator RTL introduces coverage challenges that standard IP-block verification playbooks don't cover. What we've learned from working with AI chip startups on their first tapeouts.