Stop guessing which tests to write.
Photoniq reads your simulation coverage database and predicts the exact test vectors that will hit your remaining uncovered RTL logic — cutting directed-test writing from weeks to hours.
The coverage plateau
Random simulation runs out of ideas at 85%.
Every chip team hits it. Coverage climbs fast through the first weeks of constrained-random simulation, then flattens. The remaining 10–15% is functionally uncovered — and the only way in is directed tests written by hand.
Writing directed tests takes weeks. DV engineers read RTL, reason through corner cases, write test scenarios, iterate. It is the slowest and most error-prone part of the verification cycle. Coverage escapes at tape-out are almost always in this zone.
Photoniq breaks the plateau. Our model reads your existing coverage database and predicts the specific test vectors that will reach uncovered logic — ranked by likelihood of finding new bugs.
Coverage prediction
Know where you're exposed before tape-out.
Random simulation leaves a predictable residue: rarely-toggled FSM state transitions, out-of-bounds addressing sequences, multi-cycle protocol edge cases. Photoniq's model was trained on RTL coverage patterns from real designs — it learns which code constructs correlate with hard-to-reach logic and which input sequences reliably unlock those paths.
The output is a ranked list: these specific test scenarios will toggle these specific uncovered bins, ordered by predicted bug-discovery probability. Not a hint — a scored, actionable manifest.
Yield impact modeling
Layout choices have a cost. Now you can see it.
Every floorplan decision — block aspect ratio, density allocation, metal layer assignment — affects manufacturing yield. Photoniq estimates the yield impact of layout choices using process-specific defect density models, giving your physical design team an early signal that would otherwise only surface at post-silicon analysis.
Correlate layout regions with functional coverage holes. When an uncovered logic block sits in a high-yield-risk zone, your triage priority is obvious. We do not replace your DRC or LVS toolchain — we flag which coverage gaps carry compounded yield risk.
Simulator integration
Fits in your existing flow.
Photoniq plugs into VCS, Questa (formerly ModelSim), Xcelium, and Riviera-PRO via standard UCDB and SAIF export formats. No changes to your simulation scripts, no proprietary instrumentation.
One CLI command exports your coverage database and sends it to the Photoniq analysis engine. Results return as a structured JSON manifest you can version-control alongside your RTL — and diff across simulation runs to track closure progress.
$ phnq analyze --ucdb sim.ucdb --rtl ./src
Photoniq v0.9.1 · Connecting to analysis engine...
✓ UCDB loaded: 12,847 coverage bins across 34 modules
✓ RTL indexed: 48,213 lines across ./src/**/*.sv
Running gap analysis...
⚠ 3 critical uncovered regions detected
Generating ranked test recommendations...
✓ Analysis complete in 4.2s
Results → ./phnq-manifest.json (10 recommendations)
$ cat phnq-manifest.json | jq '.recommendations[0]'
{
"test_scenario": "lsu_buffer_misaligned_access_edge",
"target_module": "lsu_buffer",
"confidence": 0.94,
"coverage_bins_hit": ["misaligned_word_rd", "misaligned_dword_wr"],
"suggested_constraints": { ... }
}
Practitioner feedback
From the DV floor
We closed the last 8% of functional coverage in two days instead of two weeks. The ranked test list was immediately actionable — we ran the top five recommendations and hit every flagged coverage gap on the first pass.
The yield impact estimates matched what our DRC tool flagged two weeks later. First time I've seen that correlation outside of tape-out post-analysis. It changes how we think about floorplan review in the verification phase.