Abstract visualization of a photonic integrated circuit layout with waveguide paths and verification status overlay markers
Silicon Photonics EDA

Verify before
you tape out.

Photoniq runs layout-versus-schematic and optical loss verification on your PIC design. Catch mode-mismatch and coupling errors that SPICE can't see — before the mask order.

Request Access Read the Docs
$100K+ Typical mask re-spin cost. One mode-mismatch bug can send you back to fab.
SPICE gap SPICE models electron flow. Waveguide physics — coupling loss, mode fields — are invisible to SPICE LVS.
LVS gap Existing EDA LVS tools weren't built for PICs. There's no standard photonic LVS in the tape-out flow.
Error Detection

What Photoniq catches

Every violation Photoniq reports is a class of error that has caused a real PIC tape-out to fail. No false positives from physics approximations.

MODE_MISMATCH
Width discontinuity at waveguide junction exceeds eigenmode overlap threshold. TE0 power coupling drops below PDK spec.
COUPLING_INEFFICIENCY
Coupling gap deviation from PDK-modeled nominal exceeds tolerance. Insertion loss budget violation.
WAVEGUIDE_WIDTH_VIOLATION
Routing segment width outside PDK single-mode window. Multimode excitation risk at this width.
TAPER_ANGLE_ERROR
Taper half-angle exceeds adiabatic limit for this waveguide geometry. Mode conversion efficiency reduced.
ROUTING_SCHEMATIC_MISMATCH
GDS layout connectivity does not match extracted SPICE netlist. LVS violation — port connection missing.
photoniq verify — output.log 
Photoniq v1.4.2  job=PNQ-2A8F  pdk=AIM_300mm_v3.1
─────────────────────────────────────────────────
PASS  DRC  cell:TOP  rules:248  violations:0
PASS  LVS  cell:TOP  ports:14  connected:14
WARN  COUPLING  cell:ring_add_drop/coupler_N
        gap=185nm  nominal=200nm  delta=-15nm
        severity:WARNING  loss_excess:+0.8dB
FAIL  MODE_MISMATCH  cell:edge_coupler_v2/wg_taper
        width_in=500nm  width_out=220nm
        overlap=0.71  threshold=0.85
        severity:ERROR  layer:Si_core  coord:(4823,2190)um
WARN  TAPER_ANGLE  cell:splitter_1x2/branch_L
        half_angle=4.8°  adiabatic_limit=3.2°
        severity:WARNING
PASS  OPTICAL_LOSS  budget:12.4dB  limit:14.0dB
─────────────────────────────────────────────────
SUMMARY  errors:1  warnings:2  passed:4
STATUS: FAIL — 1 blocking error must be resolved
Workflow

Three steps from GDS to verified

STEP 01

Import your GDS layout + schematic netlist

Point Photoniq at your GDS-II or OASIS file and your SPICE netlist. Specify your PDK. No GDS flattening required.

STEP 02

Photoniq runs LVS + optical loss engine

LVS engine checks layout connectivity against schematic. Optical loss engine checks waveguide physics against PDK rules. 5–30 minutes depending on circuit size.

STEP 03

Get a structured verification report

JSON + HTML report showing every violation with cell path, layer, GDS coordinate, severity, and suggested fix. Ready for fab submission review.

See full workflow
PDK-native verification — supported process design kits
IMEC iSiPP50G AIM Photonics 300mm PDK AMF Si-Photonics Applied Nanotools NanoSOI Ligentec AN800 Custom PDK via Config API

"Photoniq flagged three mode-mismatch violations in our edge coupler array at the taper-to-waveguide junction. We caught those on the first iteration instead of after a $180K re-spin. The JSON report gave us the exact GDS coordinates — we fixed the taper geometry in an afternoon."

Yuki Tanaka Senior PIC Design Engineer — silicon photonics startup

Run your first verification in under a day.

Works with KLayout, Cadence Virtuoso, and Python-based PIC design flows.

Request Access