Optical fiber systems engineers have used loss budget analysis as a design discipline for decades. You define a power level at the transmitter, subtract every loss contribution along the signal path — fiber attenuation, connector loss, splice loss, splitter excess loss — and confirm that enough power arrives at the receiver to meet the required BER. The discipline is so embedded in fiber systems work that skipping it before deploying a link would seem professionally irresponsible.
In PIC design, the equivalent discipline is less consistently practiced. Part of the reason is tooling: unlike fiber systems, where component loss specifications come with calibrated data sheets, PIC components live in a PDK whose loss models are process-dependent and vary with foundry run conditions. Another part is workflow: PIC designers often simulate key components in isolation and trust that the full-circuit behavior follows from composition, without explicitly accounting for every inter-component junction and routing segment.
The result is that loss budget surprises at characterization are common enough to be considered a normal part of the PIC development cycle. They shouldn't be.
The Loss Budget Concept Applied to PICs
A PIC optical loss budget starts with a defined signal path: from the input fiber coupling point, through every optical element in the circuit, to the output port or detector. For each segment of that path, you assign a loss contribution based on the best available model. The sum of all contributions gives you the expected on-chip insertion loss for that path.
Loss sources in a PIC fall into several categories:
- Fiber-to-chip coupling loss: For grating couplers in standard SOI processes, insertion loss is typically in the 2–5 dB range per coupling point. Edge couplers with inverse tapers can achieve 1–2 dB, but depend on fiber alignment tolerance and spot size matching. This is usually the largest single loss term in the budget.
- Waveguide propagation loss: Strip waveguides in well-characterized 220 nm SOI processes exhibit propagation loss in the range of 2–3 dB/cm. Rib waveguides may be lower (1–2 dB/cm) due to reduced sidewall scattering. Routing length directly multiplies this contribution.
- Bend loss: Bends below the process minimum bend radius introduce radiation loss. Above the minimum, bend loss is negligible. PDK minimum bend radii for strip waveguides in 220 nm SOI are typically in the 5–10 μm range for sub-0.1 dB/bend loss.
- Junction and interface loss: Mode mismatch at cell boundaries, waveguide crossings, and Y-junction excess loss. Each crossing in a well-designed PDK adds typically 0.05–0.3 dB; junction mismatches add variable loss depending on width discontinuity.
- Component excess loss: Splitters, MMIs, and directional couplers have excess loss beyond the theoretical splitting ratio. PDK datasheets specify this; it must be included in the budget.
Why the Budget Must Be Built at the Layout Level
Here is the critical point that distinguishes a pre-tape-out loss budget from a schematic-level estimate: the layout introduces loss contributions that the schematic never captures.
Consider routing path length. In a schematic, two components are connected by a wire symbol with no physical length. In the layout, the actual waveguide connecting them may meander through 5 mm of routing to avoid obstacles, adding propagation loss that the schematic never modeled. Unless someone explicitly measured the total routed waveguide length per path and applied the propagation loss figure, that loss is invisible at the schematic level.
The same is true for crossings. A schematic may show two paths as independent. In the layout, to achieve routing feasibility, one path may cross the other multiple times using waveguide crossing structures. Each crossing adds excess loss and back-reflection. The budget needs to count actual crossings in the routed layout, not crossing count from the schematic.
And for junction violations — if the layout contains abrupt width mismatches at cell boundaries (a common issue, as discussed in earlier posts in this series), those contribute loss that appears nowhere in the schematic-level model.
A layout-level loss budget extraction reads the actual GDS geometry: waveguide path lengths, crossing instances, coupling structures, and cell boundary junctions, then aggregates these against PDK loss models to produce a per-path loss estimate grounded in what was actually drawn, not what was intended.
Constructing the Budget: A Worked Example Structure
For a simple two-port modulator path — grating coupler input → routing waveguide → modulator → routing waveguide → grating coupler output — a loss budget table would look like this:
| Loss Source | Count | Per-Unit Loss | Total Loss |
|---|---|---|---|
| Grating coupler (in) | 1 | 3.5 dB | 3.5 dB |
| Input routing waveguide | 3.2 mm | 2.5 dB/cm | 0.8 dB |
| Waveguide crossings | 4 | 0.15 dB/crossing | 0.6 dB |
| Cell junction mismatches | 2 | 0.3 dB | 0.6 dB |
| Modulator excess loss | 1 | 1.5 dB | 1.5 dB |
| Output routing waveguide | 2.8 mm | 2.5 dB/cm | 0.7 dB |
| Grating coupler (out) | 1 | 3.5 dB | 3.5 dB |
| Total insertion loss | 11.2 dB |
The numbers above are illustrative structure, not prescriptive values — actual PDK specs vary by process. The point is the structure: every loss contribution has a source, a count extracted from the layout, and a per-unit value from the PDK model.
Where Loss Budget Analysis Breaks Down
We're not saying that a layout-extracted loss budget gives you a precise prediction of on-wafer insertion loss. Several sources of uncertainty limit accuracy:
Process variation: PDK loss models are typically specified at nominal process conditions. Actual propagation loss can vary ±0.5–1 dB/cm depending on etch uniformity, sidewall roughness variation across the wafer, and oxide cladding quality. For long routing paths, this uncertainty compounds.
Temperature dependence: Silicon has a non-trivial thermo-optic coefficient (~1.8 × 10⁻⁴ /°C). Ring resonator resonance positions shift substantially with temperature, changing insertion loss at the designed operating point. A loss budget at room temperature says nothing about performance at operating temperature.
Model accuracy: PDK component models are fit to characterization data from past fabrication runs. If the component you're using is new, or if the PDK characterization data is sparse, the model may not accurately represent the fabricated component.
The value of a pre-tape-out loss budget is not prediction accuracy — it's early detection of budget violations. If the extracted budget shows the total insertion loss exceeds your system requirement by 3 dB, you know before tape-out that either the design needs rework or the system requirement needs to be revised. That's a productive discovery regardless of the ±1 dB uncertainty in the model.
Integrating Loss Budget Into the Tape-Out Sign-Off Gate
The loss budget analysis works best when it is part of the formal tape-out sign-off checklist, not an optional post-design review step. Specifically:
- Each signal path with a defined optical power budget must have an extracted loss estimate from the final GDS revision.
- Any path where the estimated loss exceeds the budget threshold (typically set with a margin against system requirement) blocks tape-out pending design review.
- Loss contributions from layout violations — junction mismatches, crossing violations, bend radius violations — are counted in the budget as conservative penalty values, not as zero.
This transforms the loss budget from an analytical exercise into a machine-checkable gate condition. The same structured report that flags DRC and LVS violations can carry loss budget results: path name, estimated loss, budget limit, pass/warn/fail status. The designer and tape-out engineer see the complete verification picture in one report rather than assembling it from separate simulation and manual review outputs.
For PIC design teams preparing frequent tape-outs — whether multi-project wafer slots or dedicated runs — building this discipline into the flow pays compounding returns. Each tape-out that passes a documented loss budget produces a comparison point against measured on-wafer results. Over time, the gap between pre-tape-out estimates and measured performance narrows as the model parameters are refined with actual fabrication data from the team's specific foundry runs and process corners.
Practical First Steps
If your current tape-out flow doesn't include a formal optical loss budget, the most effective starting point is not to build a complete automated extraction system immediately. Start with a manual budget for your most critical signal paths — the ones where a 3 dB loss error would break the system application. Extract routing path lengths from the layout, count waveguide crossings, identify any known junction mismatches, and apply PDK propagation loss and coupling loss numbers.
The exercise will almost certainly reveal at least one path where the accumulated loss exceeds what the schematic-level simulation assumed. That discovery alone justifies the time spent, and creates the motivation to automate the process for future tape-outs through integration with layout verification tooling that extracts these quantities directly from the GDS geometry.