Every CMOS engineer knows the ritual: you tape out, LVS runs, DRC passes, and the design moves forward. The layout-versus-schematic check compares what you drew against what you intended to build, and a clean sign-off means the two match. It works because SPICE, the underlying model for almost all electronic LVS tools, captures the physics that matter for electrons: resistance, capacitance, transistor gate geometry, interconnect parasitics.
Photonics is different in ways that make SPICE-based LVS structurally inadequate for PIC tape-out. This isn't a tooling gap that more careful use of existing software can close — it reflects a fundamental mismatch between what SPICE models and what photons actually do in a waveguide.
What SPICE-Based LVS Actually Checks
In a conventional CMOS LVS flow, extraction reads the drawn polygons in GDS-II, identifies transistors and metal interconnects by their layer combinations, and reconstructs a connectivity netlist. That netlist is then compared node-by-node against the schematic. Parasitics — resistance of metal lines, capacitance between layers — get extracted as numerical values. The model is electrical: current flows, voltage is defined at each node, and every component has a two-terminal or multi-terminal electrical behavior that SPICE can simulate.
This model works for CMOS because the electrical quantities that matter — drain current, threshold voltage, IR drop — map cleanly onto polygon geometry. The width and length of a MOS gate determine W/L. Metal width and layer determine resistance per square. The physics and the geometry are coupled in ways that straightforward extraction algorithms can handle.
The Fundamental Problem: Optical Modes Are Not Nodes
A silicon waveguide carrying 1550 nm light is not an electrical conductor. The "signal" propagating through it is a transverse electromagnetic mode — a spatial distribution of the electric field that exists in a cross-section defined by the waveguide width, height, and cladding geometry. The effective refractive index n_eff determines the phase velocity. The propagation constant β = (2π/λ) × n_eff determines how quickly phase accumulates along the waveguide length.
None of these quantities appear in a SPICE netlist. A SPICE node has a voltage. A waveguide port has a mode field profile, a polarization state, and a propagation direction. When two waveguides connect at a junction, the optical signal transfer is governed by the overlap integral between the mode profiles of the two waveguides — not by any electrical boundary condition.
This is the root of the problem. If a designer connects a 500 nm wide single-mode waveguide to a 450 nm wide waveguide with an abrupt junction — no taper — SPICE sees two connected nets with a valid electrical path. The LVS pass/fail status is unaffected. But from a photonics standpoint, the mismatch in mode field diameter between those two widths causes reflection and scattering loss. Depending on the wavelength and waveguide geometry, the loss can range from small fractions of a dB to several dB. SPICE does not know this happened.
Three Failure Classes SPICE Misses Entirely
1. Mode mismatch at abrupt junctions
The mode field supported by a waveguide cross-section changes with width. In a standard 220 nm thick SOI platform, a single-mode waveguide at 1550 nm supports a TE00 mode with a characteristic field distribution. That distribution shifts as width changes. An abrupt transition — where two waveguide segments of different widths meet without a taper — creates a modal discontinuity. The coupling efficiency at the junction is the squared overlap integral of the two mode profiles, which is strictly less than 1 for any width mismatch. Standard LVS, looking only at electrical connectivity, sees a valid connection and reports no violation.
2. Coupling gap violations in evanescent structures
Directional couplers, ring resonator bus-ring gaps, and MMI structures all rely on the evanescent field extending from one waveguide into another. The coupling coefficient depends exponentially on the gap distance. A gap that is 20 nm narrower than PDK specification might double the coupling coefficient; a 30 nm wider gap might reduce it by half. Neither condition has any electrical signature. SPICE-based LVS checks that both waveguides are present in the layout and that they are connected in the schematic — but it has no concept of the physical gap between them, let alone whether that gap is within the foundry-specified tolerance for the intended coupling ratio.
3. Waveguide routing that creates unintended evanescent coupling
In dense PIC layouts, waveguides that cross or run parallel too closely will exchange optical power through the evanescent field even when no coupling was intended. Two waveguides running in parallel at 2 μm separation for 100 μm of shared length can act as an accidental coupler with measurable cross-talk, depending on the waveguide geometry and wavelength. SPICE-based LVS sees two separate electrical nets — correctly, from its perspective — and issues no warning. The unintended coupling is invisible to any check that doesn't model field overlap.
What Photonic LVS Needs Instead
A verification framework that actually catches optical failures must operate on a different model. Instead of comparing electrical connectivity, it needs to compare optical connectivity: which ports connect to which, with what modal character, at what polarization, and through what pathway. Instead of checking component existence, it needs to check whether the geometric parameters of each component — waveguide width at each junction, gap at each coupling region, taper angle and length — are within the bounds specified by the PDK for correct optical behavior.
This is fundamentally a geometric rule check combined with an optical topology check. The "schematic" being compared against is not a SPICE netlist but an optical circuit description that specifies modal connectivity. The extraction pass that converts GDS-II geometry into a verifiable structure needs to identify optical components by their polygon shapes, not by their layer-combination equivalents to transistors and resistors.
We're not saying SPICE-based LVS is worthless for PIC designs — it remains useful for the electronic control circuitry on co-integrated photonic-electronic platforms. Many silicon photonics processes include doped waveguide modulators, germanium photodetectors, and heater elements that have real electrical models. For those components, conventional LVS checks apply and should run. The gap is the optical layer: the waveguide routing, the coupling structures, the optical ports, and the mode-critical junctions. These need a separate verification pass that SPICE-based tools were never designed to perform.
A Concrete Scenario
Consider a 4-channel WDM demux built around an arrayed waveguide grating on a standard 220 nm SOI platform. The AWG has input/output waveguides at 500 nm width, a free propagation region, and an array of waveguides ranging from ~490 nm to ~520 nm in width across the array. The schematic shows the AWG block connected to four output ring-resonator drop filters, each implemented as a 10 μm radius ring with a 200 nm coupling gap.
A SPICE-based LVS run on this design will verify that the four output waveguides from the AWG connect to the four ring bus waveguides, that each ring has a drop port connected to the output waveguide in the schematic, and that there are no unconnected ports. It will pass, assuming the designer got the connectivity right. It will not check: whether the AWG waveguide width at the free propagation region interface transitions through a proper taper, whether the 200 nm coupling gap is within 10% of PDK specification (tight tolerances apply here), whether any two bus waveguides run closer than 3 μm for more than 20 μm (a cross-talk risk in many PDKs), or whether the output waveguide widths at the ring-to-waveguide junction are matched.
These are the checks that prevent the re-spin. Not SPICE.
Implications for Tape-Out Flows
The practical consequence is that PIC design teams running conventional CMOS-heritage EDA flows have a structural verification gap at tape-out. The LVS sign-off they receive means the optical topology is connected as drawn — it says nothing about whether the connections are optically correct. Teams discover this either through on-wafer characterization after fabrication or through careful manual review before tape-out, both of which are expensive in different ways.
Adding a dedicated photonic verification pass — one that operates on optical connectivity, modal geometry, and coupling-rule compliance — closes this gap before GDS submission. The check doesn't replace simulation; it doesn't run FDTD or EME. It operates at the same abstraction level as DRC and LVS: given the drawn geometry and the PDK rules, does this design comply? The answer is either a pass, a warning, or a violation — in a structured report that can gate tape-out submission just as DRC and LVS currently do.
For teams already investing in simulation to validate device performance, verification fills a different role: it confirms that the layout matches the intent specified in the PDK, at every junction and coupling structure in the circuit, without requiring simulation of each instance individually. At the scale of a full-chip PIC layout with dozens of waveguide routes and coupling structures, that coverage difference is significant.